重庆览山汽车电子有限公司

1. Responsible for the entire process of SOC/ASIC chips from netlist to tap out;

2. Negotiate with front-end designers to solve problems encountered during the physical design process and optimize design solutions;

3. Timely write various design documents and standardized materials to achieve resource and experience sharing.

1. Bachelor's degree or above in microelectronics, communication engineering, integrated circuits, automation and related majors;

2. Familiar with the entire process of implementing digital chips (RTL to GDS);

3. Proficient in Physical Design, including floorplan, IO planning, power planning, placement, CTS, routing, timing fix, ECO Wait;

4. Proficient in one or more scripting languages, proficient in physical verification, including DRC/LVS/ERC/Ant/DFM, etc;

5. Passionate about work, responsible, meticulous in work, and strong in learning ability.

Responsible for ASIC chip design delivery and providing relevant process/engineering technical support, responsible for the quality, progress, and cost of delivered products.

1. Responsible for the detailed physical design and verification of ASIC chips from RTL to GDSII, including physical architecture planning, layout and routing, power planning, clock tree synthesis, timing convergence, physical verification, power network analysis, and low-power design. Provide competitive solutions in PPA (performance, power consumption, cost) achievement, design, and process window matching;

2. Responsible for ASIC chip DFT design and validation, accountable for testing costs, testing coverage, failure rates, and delivery times, providing competitive testing vectors and solutions, carrying out testing diagnostics, assisting in rapid process and testing problem localization.

1. Bachelor's degree or above in microelectronics, computer science, communication engineering, automation and related majors.

2. Priority will be given to those who meet any of the following conditions:

(1) Proficient in deep sub micron backend physical design process, familiar with digital chip physical design tools such as Synopsys/Cadence, physical verification tools such as Calibre, and timing verification tools such as PT;

(2) Familiar with digital chip DFT or front-end logic design processes, familiar with digital circuit hardware description design languages such as Verilog, and knowledgeable or able to use Synopsys or Mentor related tools;

(3) The research direction is related to advanced semiconductor process technology and integrated development.

3. Passionate about work, responsible, meticulous in work, and strong in learning ability.

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